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k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 1 document title 128k x8 bit low power and low voltage cmos static ram revision history remark preliminary final final history initial draft finalize - increased i sb , i dr commercial part = 10 m a industrial part = 20 m a revise - change speed bin km68v1000c family: 70/85ns ? 70/100ns km68u1000c family: 70/100ns ? 85/100ns - improved operating current: 40ma ? 35ma - improved power dissipation p d : 0.7w ? 1.0w - improved standby current extended/industrial: 20 ? 10 m a - vil: 0.4v ? 0.6v draft data july 3, 1996 december 16, 1996 november 25, 1997 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserves the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision no. 0.0 1.0 2.0
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 2 128k x8 bit low power and low voltage cmos static ram general description the k6t1008v2c and k6t1008u2c families are fabricated by samsung s advanced cmos process technology. the fami- lies support various operating temperature ranges and have various package types for user flexibility of system design. the families also supports low data retention voltage for battery back-up operation with low data retention current. features process technology: 0.4 m m cmos organization: 128k x8 power supply voltage: k6t1008v2c family: 3.0~3.6v k6t1008u2c family: 2.7~3.3v low data retention voltage: 2v(min) three state output and ttl compatible package type: 32-sop-525, 32-tsop1-0820f/r, 32-tsop1-0813.4f/r name function cs 1 , cs 2 chip select inputs oe output enable input we write enable input a 0 ~a 16 address inputs i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground n.c no connection product family product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6t1008v2c-b commercial(0~70 c) 3.0~3.6v 70/100ns 10 m a 35ma 32-sop 32-tsop1-f/r 32-stsop1-f/r k6t1008u2c-b 2.7~3.3v 85/100ns k6t1008v2c-d extended(-25~85 c) 3.0~3.6v 70/100ns k6t1008u2c-d 2.7~3.3v 85/100ns k6t1008v2c-f industrial(-40~85 c) 3.0~3.6v 70/100ns k6t1008u2c-f 2.7~3.3v 85/100ns functional block diagram pin description 32-tsop type1-reverse a11 a9 a8 a13 we cs2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32- s tsop type1-forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n.c a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 cs2 we a13 a8 a9 a11 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-sop a11 a9 a8 we a13 cs2 vcc a15 nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-tsop samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 1024 rows 128 8 columns i/o circuit column select clk gen. row select a10 a0 a1 a2 a3 a11 a9 i/o 1 data cont i/o 8 v cc v ss a4 a5 a6 a7 a8 a12 a14 a13 a15 a16 cs 1 we oe control logic cs2 32- s tsop
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 3 product list commercial temperature products (0~70 c) extended temperature products (-25~85 c) industrial temperature products (-40~85 c) part name function part name function part name function k6t1008v2c-gb70 k6t1008v2c-gb10 k6t1008v2c-tb70 k6t1008v2c-tb10 k6t1008v2c-rb70 k6t1008v2c-rb10 k6t1008u2c-gb85 k6t1008u2c-gb10 k6t1008u2c-tb85 k6t1008u2c-tb10 k6t1008u2c-rb85 k6t1008u2c-rb10 k6t1008v2c-yb70 k6t1008v2c-yb10 k6t1008v2c-nb70 k6t1008v2c-nb10 k6t1008u2c-yb85 k6t1008u2c-yb10 k6t1008u2c-nb85 k6t1008u2c-nb10 32-sop, 70ns, 3.3v 32-sop, 100ns, 3.3v 32-tsop f, 70ns, 3.3v 32-tsop f, 100ns, 3.3v 32-tsop r, 70ns, 3.3v 32-tsop r, 100ns, 3.3v 32-sop, 85ns, 3.0v 32-sop, 100ns, 3.0v 32-tsop f, 85ns, 3.0v 32-tsop f, 100ns, 3.0v 32-tsop r, 85ns, 3.0v 32-tsop r, 100ns, 3.0v 32-stsop f, 70ns, 3.3v 32-stsop f, 100ns, 3.3v 32-stsop r, 70ns, 3.3v 32-stsop r, 100ns, 3.3v 32-stsop f, 85ns, 3.0v 32-stsop f, 100ns, 3.0v 32-stsop r, 85ns, 3.0v 32-stsop r, 100ns, 3.0v k6t1008v2c-gd70 k6t1008v2c-gd10 k6t1008v2c-td70 k6t1008v2c-td10 k6t1008V2C-RD70 k6t1008v2c-rd10 k6t1008u2c-gd85 k6t1008u2c-gd10 k6t1008u2c-td85 k6t1008u2c-td10 k6t1008u2c-rd85 k6t1008u2c-rd10 k6t1008v2c-yd70 k6t1008v2c-yd10 k6t1008v2c-nd70 k6t1008v2c-nd10 k6t1008u2c-yd85 k6t1008u2c-yd10 k6t1008u2c-nd85 k6t1008u2c-nd10 32-sop, 70ns, 3.3v 32-sop, 100ns, 3.3v 32-tsop f, 70ns, 3.3v 32-tsop f, 100ns, 3.3v 32-tsop r, 70ns, 3.3v 32-tsop r, 100ns, 3.3v 32-sop, 85ns, 3.0v 32-sop, 100ns, 3.0v 32-tsop f, 85ns, 3.0v 32-tsop f, 100ns, 3.0v 32-tsop r, 85ns, 3.0v 32-tsop r, 100ns, 3.0v 32-stsop f, 70ns, 3.3v 32-stsop f, 100ns, 3.3v 32-stsop r, 70ns, 3.3v 32-stsop r, 100ns, 3.3v 32-stsop f, 85ns, 3.0v 32-stsop f, 100ns, 3.0v 32-stsop r, 85ns, 3.0v 32-stsop r, 100ns, 3.0v k6t1008v2c-gf70 k6t1008v2c-gf10 k6t1008v2c-tf70 k6t1008v2c-tf10 k6t1008v2c-rf70 k6t1008v2c-rf10 k6t1008u2c-gf85 k6t1008u2c-gf10 k6t1008u2c-tf85 k6t1008u2c-tf10 k6t1008u2c-rf85 k6t1008u2c-rf10 k6t1008v2c-yf70 k6t1008v2c-yf10 k6t1008v2c-nf70 k6t1008v2c-nf10 k6t1008u2c-yf85 k6t1008u2c-yf10 k6t1008u2c-nf85 k6t1008u2c-nf10 32-sop, 70ns, 3.3v 32-sop, 100ns, 3.3v 32-tsop f, 70ns, 3.3v 32-tsop f, 100ns, 3.3v 32-tsop r, 70ns, 3.3v 32-tsop r, 100ns, 3.3v 32-sop, 85ns, 3.0v 32-sop, 100ns, 3.0v 32-tsop f, 85ns, 3.0v 32-tsop f, 100ns, 3.0v 32-tsop r, 85ns, 3.0v 32-tsop r, 100ns, 3.0v 32-stsop f, 70ns, 3.3v 32-stsop f, 100ns, 3.3v 32-stsop r, 70ns, 3.3v 32-stsop r, 100ns, 3.3v 32-stsop f, 85ns, 3.0v 32-stsop f, 100ns, 3.0v 32-stsop r, 85ns, 3.0v 32-stsop r, 100ns, 3.0v functional description 1. x means don t care(must be in high or low status.) cs 1 cs 2 oe we i/o pin mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect re liability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v - voltage on vcc supply relative to v cc -0.3 to 4.6 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t1008v2c-b/k6t1008u2c-b -25 to 85 c k6t1008v2c-d/k6t1008u2c-d -40 to 85 c k6t1008v2c-f/k6t1008u2c-f soldering temperature and time t solder 260 c, 10sec (lead only) - -
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 4 capacitance 1) (f=1mhz, ta=25 c) 1 . capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 6 pf input/output capacitance c io v io =0v - 8 pf recommended dc operating conditions 1) 1. commercial product: t a =0 to 70 c, unless otherwise specified extended product: t a =-25 to 85 c, unless otherwise specified industrial product: t a =-40 to 85 c, unless otherwise specified 2. overshoot: v cc +3.0v in case of pulse width 30ns 3. undershoot: -3.0v in case of pulse width 30ns 4. overshoot and undershoot is sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6t1008v2c family k6t1008u2c family 3.0 2.7 3.3 3.0 3.6 3.3 v ground vss all family 0 0 0 v input high voltage v ih k6t1008v2c, k6t1008u2c family 2.2 - vcc+0.3 2) v input low voltage v il k6t1008v2c, k6t1008u2c family -0.3 3) - 0.6 v dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il, v io =vss to vcc -1 - 1 m a operating power supply i cc i io =0ma, cs 1 =v il , cs 2 =v ih , v in =v il or v ih , read - 2 5 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 1 0.2v, cs 2 3 v cc -0.2v, v in 0.2v or v in 3 v cc -0.2v read - 1.5 5 ma write 10 15 i cc2 cycle time=min, 100% duty, i io =0ma, cs 1 =v il , cs 2 =v ih , v in =v il or v ih - 25 35 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.2 - - v standby current(ttl) i sb cs 1 =v ih, cs 2 =v il , other inputs=v il or v ih - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v, other inputs=0~vcc - 0.3 10 m a
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 5 c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage:1.5v output load(see right): c l =100pf+1ttl ac characteristics (commercial product:t a =0 to 70 c, extended product:t a =-25 to 85 c, industrial product: t a =-40 to 85 c k6t1008v2c family: vcc=3.0~3.6v, k6t1008u2c family: vcc=2.7~3.3v) parameter list symbol speed bins units 70ns 85ns 100ns min max min max min max read read cycle time t rc 70 - 85 - 100 - ns address access time t aa - 70 - 85 - 100 ns chip select to output t co1 , t co2 - 70 - 85 - 100 ns output enable to valid output t oe - 35 - 40 - 50 ns chip select to low-z output t lz 10 - 10 - 10 - ns output enable to low-z output t olz 5 - 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 0 30 ns output disable to high-z output t ohz 0 25 0 25 0 30 ns output hold from address change t oh 10 - 15 - 15 - ns write write cycle time t wc 70 - 85 - 100 - ns chip select to end of write t cw 60 - 70 - 80 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 60 - 70 - 80 - ns write pulse width t wp 55 - 60 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 30 0 30 ns data to write time overlap t dw 30 - 35 - 40 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 5 - ns data retention characteristics 1. cs 1 3 vcc-0.2v , cs 2 3 v cc -0.2v, or cs 2 0.2v item symbol test condition 1) min typ max unit vcc for data retention v dr cs 1 1) 3 vcc-0.2v 2.0 - 3.6 v data retention current i dr vcc=3.0v, cs 1 3 vcc-0.2v , cs 2 3 v cc -0.2v, or cs 2 0.2v - 0.3 5 m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 7 timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 8 data retention wave form cs 1 controlled v cc 3.0/2.7v 1) 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc -0.2v t sdr t rdr timing waveform of write cycle(3) (cs 2 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low: a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr(1) applied in case a write ends as cs 1 or we going high t wr(2) applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 3.0/2.7v 1) 0.4v v dr cs 2 gnd data retention mode t sdr t rdr 1. 3.0v for k6t1008v2c family, 2.7v for k6t1008u2c family cs 2 0.2v
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 9 package dimensions units: millimeter(inch) 32 pin plastic small outline package (525mil) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 10 #32 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 0 . 1 0 #1 13.40 0.20 0.528 0.008 #17 #16 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 m a x #32 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45~0.75 0.018~0.030 13.40 0.20 0.528 0.008 #17 #16 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 0 . 0 0 4 0 . 1 0 m a x 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45~0.75 0.018~0.030 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 typ 0.25 0.010 32 pin thin small outline package type i (0813.4f) package dimensions 32 pin thin small outline package type i (0813.4r) units: millimeter(inch)
k6t1008v2c, k6t1008u2c family cmos sram revision 2.0 november 1997 11 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 package dimensions 32 pin thin small outline package type i (0820r) #32 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 units: millimeter(inch)

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